Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), interconnect lines (wires) and programmable interconnection points (PIPs), and so forth.
The programmable tiles are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
FIG. 1 is a simplified illustration of an exemplary PLD, e.g., the Virtex®-4 FPGA available from Xilinx, Inc. The PLD of FIG. 1 includes columns of logic tiles including configurable logic blocks (CLBs) and input/output blocks (IOBs), and programmable interconnect tiles (INTs) that are used to programmably interconnect the logic tiles. Surrounding the array are terminating tiles (TERMs). In the pictured embodiment, the interconnect tiles are identical to one another. This uniformity makes the architecture more amenable to change, and also easier to maintain. Additionally, this approach reduces the design time for a PLD, because design teams designing logic tiles can assume that the connectivity of the interconnect tiles feeding the logic tiles is fixed. Thus, for example, some PLDs also include additional logic tiles with special purposes (not shown), e.g., DLLs, block RAM, and so forth. In the Virtex-4 FPGA, these additional logic tiles also use the same interconnect tiles as the CLBs and IOBs.
Interconnect tiles in the Virtex-4 device include two types of connectivity. One type is the connectivity across tiles, which includes “doubles” (wires two tiles long), “hexes” (wires six tiles long), and “longs” (wires 24 tiles long), for example. The other type is the connectivity to the logical pins of the adjacent logic tile, which can include, for example, connections to input multiplexers and output multiplexers of the logic tile.
Some FPGAs do not use the same interconnect tile for all logic tile types. For example, it may be more area efficient to customize the interconnect tile for each type of logic tile, by only including the connectivity required by that type of logic tile. While this approach may save die area, it also requires more design hours and reduces the symmetry of the FPGA, which may have a negative impact on the efficiency of the FPGA implementation software.
FPGA implementation software typically includes a mapper (which maps the user logic to programmable elements of the FPGA), a placer (which places the mapped elements into logic tiles on the FPGA), and a router (which routes signals between the logic tiles using the interconnect tiles). The tools may also include a physical synthesis tool, which inputs a user design and outputs a netlist representation of the design, suitable for mapping. Each of these software tools can provide a better result (e.g., a design implementation with a faster operating frequency) if provided with accurate timing delays for the various elements of the FPGA.
While worst-case timing delays for each net can be calculated using specified delay values for every individual component of the net, such calculations can be very expensive in terms of computing time and power. Therefore, it is desirable to provide methods of accurately estimating timing delays in a PLD that can be used, for example, when implementing a user design in the PLD.